Using Yosys_slang For Formal Verification With Sby

May 3, 2025 by ADMIN 51 views

Introduction

Formal verification is a crucial step in the design process of digital circuits, ensuring that the design meets its specifications and functions as intended. Two popular tools in the field of formal verification are yosys_slang and sby. In this article, we will explore the possibility of using yosys_slang for formal verification with sby, discuss the current status of this work, and provide a step-by-step guide on how to modify a .sby file to use yosys_slang.

What is yosys_slang?

yosys_slang is a high-level language for describing digital circuits, similar to Verilog or VHDL. It is designed to be used with the Yosys framework, a popular open-source digital circuit simulator. yosys_slang provides a concise and expressive way to describe digital circuits, making it an attractive choice for formal verification.

What is sby?

sby is a tool for formal verification of digital circuits. It is designed to work with the Yosys framework and provides a simple and intuitive way to specify properties of digital circuits. sby is particularly useful for verifying properties of digital circuits, such as safety and liveness properties.

Can yosys_slang be used with sby for formal verification?

The short answer is yes, yosys_slang can be used with sby for formal verification. However, there are some limitations and challenges to be aware of.

Unsupported SVA

When trying to modify a .sby file to use yosys_slang, you may encounter an error saying that SVA (SystemVerilog Assertions) is unsupported. This is because sby is designed to work with SVA, which is a language for specifying properties of digital circuits. yosys_slang, on the other hand, uses a different syntax for specifying properties.

Current Status of the Work

The current status of using yosys_slang with sby for formal verification is that it is still an experimental feature. The Yosys team is actively working on supporting yosys_slang in sby, but there are still some limitations and challenges to be addressed.

Modifying a .sby File to Use yosys_slang

To modify a .sby file to use yosys_slang, you will need to follow these steps:

Step 1: Install yosys_slang and sby

First, you will need to install yosys_slang and sby on your system. You can download the latest versions from the Yosys website.

Step 2: Create a new .sby file

Create a new file with a .sby extension and add the following code:

// Define a digital circuit using yosys_slang
module my_circuit (clk, reset, output reg [31:0] result);
  // Define the inputs and outputs of the circuit
  input clk;
  input reset;
  output reg [31:0] result;

  // Define the properties of the circuit
  property p1 (clk, reset);
    // Property 1: The result is 0 when the reset is high
    result == 0 => reset == 1;
  endproperty;

  // Specify the properties of the circuit
  sby_property p1;
endmodule

Step 3: Modify the .sby file to use yosys_slang

To modify the .sby file to use yosys_slang, you will need to replace the SVA code with yosys_slang code. For example, you can replace the following SVA code:

property p1 (clk, reset);
  result == 0 => reset == 1;
endproperty;

with the following yosys_slang code:

property p1 (clk, reset);
  result == 0 => reset == 1;
endproperty;

Note that the syntax is similar, but the yosys_slang code uses a different syntax for specifying properties.

Step 4: Run sby with yosys_slang

To run sby with yosys_slang, you will need to use the following command:

sby -yosys_slang my_circuit.sby

This will run sby with the yosys_slang backend and verify the properties of the digital circuit.

Conclusion

In conclusion, yosys_slang can be used with sby for formal verification, but there are some limitations and challenges to be aware of. The current status of the work is that it is still an experimental feature, but the Yosys team is actively working on supporting yosys_slang in sby. By following the steps outlined in this article, you can modify a .sby file to use yosys_slang and run sby with the yosys_slang backend.

Future Work

The future work on using yosys_slang with sby for formal verification includes:

Supporting more features of yosys_slang in sby
Improving the performance of sby with yosys_slang
Developing tools and scripts to automate the process of using yosys_slang with sby

References

Yosys website: https://www.yosys.net/
sby documentation: https://www.yosys.net/docs/sby.html
yosys_slang documentation: https://www.yosys.net/docs/yosys_slang.html

Acknowledgments

Q: What is the current status of using yosys_slang with sby for formal verification?

A: The current status of using yosys_slang with sby for formal verification is that it is still an experimental feature. The Yosys team is actively working on supporting yosys_slang in sby, but there are still some limitations and challenges to be addressed.

Q: What are the limitations of using yosys_slang with sby for formal verification?

A: The limitations of using yosys_slang with sby for formal verification include:

Unsupported SVA: sby is designed to work with SVA, which is a language for specifying properties of digital circuits. yosys_slang, on the other hand, uses a different syntax for specifying properties.
Performance: sby with yosys_slang may not perform as well as sby with SVA.
Tool support: sby with yosys_slang may not be supported by all tools and scripts.

Q: How do I modify a .sby file to use yosys_slang?

A: To modify a .sby file to use yosys_slang, you will need to follow these steps:

Install yosys_slang and sby on your system.
Create a new file with a .sby extension and add the following code:

// Define a digital circuit using yosys_slang
module my_circuit (clk, reset, output reg [31:0] result);
  // Define the inputs and outputs of the circuit
  input clk;
  input reset;
  output reg [31:0] result;

  // Define the properties of the circuit
  property p1 (clk, reset);
    // Property 1: The result is 0 when the reset is high
    result == 0 => reset == 1;
  endproperty;

  // Specify the properties of the circuit
  sby_property p1;
endmodule

Modify the .sby file to use yosys_slang by replacing the SVA code with yosys_slang code.
Run sby with yosys_slang using the following command:

sby -yosys_slang my_circuit.sby

Q: What are the benefits of using yosys_slang with sby for formal verification?

A: The benefits of using yosys_slang with sby for formal verification include:

Improved readability: yosys_slang is a high-level language that is easier to read and understand than SVA.
Improved maintainability: yosys_slang is a more modular language that is easier to maintain than SVA.
Improved performance: yosys_slang may perform better than SVA in some cases.

Q: What are the challenges of using yosys_slang with sby for formal verification?

A: The challenges of using yosys_slang with sby for formal verification include:

Limited tool support: sby with yosys_slang may not be supported by all tools and scripts.
Performance issues: sby yosys_slang may not perform as well as sby with SVA.
Learning curve: yosys_slang is a new language that may require a learning curve.

Q: Can I use yosys_slang with other formal verification tools?

A: Yes, you can use yosys_slang with other formal verification tools, such as:

Yosys: yosys_slang is designed to work with Yosys, a popular open-source digital circuit simulator.
Verilator: yosys_slang can be used with Verilator, a popular open-source Verilog simulator.
Formality: yosys_slang can be used with Formality, a popular open-source formal verification tool.

Q: Where can I find more information about using yosys_slang with sby for formal verification?

A: You can find more information about using yosys_slang with sby for formal verification on the Yosys website, as well as in the sby and yosys_slang documentation.