What Is The Optimal Temperature Range For Performing A Post-etch Residue Removal Process Using A Solvent-based Striping Solution On A 28nm FinFET Wafer With A High-k Metal Gate And A SiON Dielectric Layer, Considering The Trade-offs Between Photoresist Removal Efficiency, Metal Gate Corrosion, And Wafer Surface Roughness?

The optimal temperature range for performing a post-etch residue removal process on a 28nm FinFET wafer, considering the factors of photoresist removal efficiency, metal gate corrosion, and wafer surface roughness, is determined to be between 50°C and 70°C.

This range balances the effectiveness of the solvent-based stripping solution in removing residue without causing undue corrosion to the high-k metal gate or excessive surface roughness to the SiON dielectric layer. Specifically, a narrower sweet spot within 55°C to 65°C is suggested, as it likely offers the best compromise between efficiency and material protection. Experimental verification is recommended to confirm the exact optimal range for specific materials and solvents used.